Cross-Reference & Alternatives

Same LQFP footprint and largely register-compatible — a common second source when STM32F103 is short. Core runs to 108MHz (vs 72MHz), so recheck clock, Flash wait-states, and some HAL settings when porting.

GigaDevice positions the GD32F407 as an STM32F407-class alternative with aligned packages (LQFP100/144/BGA) and similar peripherals. A design-in alternative in most cases — verify the pin table per package and recompile/validate with the GD32 firmware library.

GigaDevice markets the GD32F2 series as a pin-to-pin and software-compatible alternative to STM32F2 (same LQFP64/100/144/176 footprints, same Cortex-M3, peripheral libraries port with minimal effort). It is not a register-identical drop-in, however: device ID, flash wait-states, and oscillator/PLL (RCU) startup timing differ, so firmware needs re-validation — treat as a design-in alternative.

The GD32F207 mirrors STM32F207’s connectivity line, including a 10/100 Ethernet MAC (MII/RMII), and shares the STM32F2 footprints. It remains a design-in alternative: Ethernet MAC registers, clock tree, and flash timing differ, so the firmware and PHY/clock init must be re-validated — do not claim a no-change Ethernet drop-in. Used with an external PHY (e.g. DM9161A/DM9162).

GigaDevice positions the GD32F1x0 value line against STM32F0, but the GD32F1x0 core is Cortex-M3 whereas STM32F030/F051 is Cortex-M0. Packages/pinouts broadly align (e.g. TSSOP20/LQFP32/48), but the different core, instruction timing, and peripheral registers make this a functional design-in alternative, not a drop-in.

The GD32F470 is GigaDevice’s high-performance Cortex-M4 (240MHz, FPU/DSP, up to 3MB flash), positioned against the STM32F4 high end (F429/F437 class), with matching LQFP100/144 and BGA176 packages. A cross-vendor design-in: clock tree, flash wait-states, and some peripherals differ, so firmware must be ported and hardware re-validated — not a no-change swap.

The STM32F405 is the STM32F407 variant without FSMC; since the GD32F407 maps to the STM32F407, it covers F405 designs (which by definition don’t use FSMC). A cross-vendor swap still needs a firmware port (clock setup, peripheral library) and board re-validation — a functional alternative.

The GD32L233 uses an Arm Cortex-M23 (64MHz) versus the STM32L0’s Cortex-M0+, with a different peripheral set and no pin/register-compatibility claim from GigaDevice — an ultra-low-power functional alternative requiring a firmware re-port and hardware re-validation.

Standard JEDEC SPI NOR pinout, command set, and QE-bit compatible — a drop-in second source for Winbond W25Q. Confirm supply voltage and page/sector size per density.

Both are JEDEC-standard 3.0V 128Mbit SPI/Quad-SPI NOR in SOIC-8/WSON-8 with identical 4KB-sector/64KB-block layout and matching QE bit (SR2 bit1), so they swap on the same footprint. The one firmware caveat: the JEDEC ID differs (Winbond EFh vs GigaDevice C8h), so any ID whitelist must add C8 40 18 and allow longer erase timeouts. Confirm voltage, density, and timing per datasheet.

Macronix MX25L, Eon EN25Q, and Cypress/Spansion S25FL 3V SPI NOR are all JEDEC-standard, sharing the SOIC-8/WSON-8 footprint and the 03h/0Bh/02h/20h/D8h command set, so GD25Q of the same density is a footprint drop-in. Note: each vendor has a different JEDEC manufacturer ID (Macronix C2h, Eon 1Ch, Spansion 01h, GigaDevice C8h) — update any ID check, and confirm QE-bit location, SFDP, voltage, density, and timing.

The GD25LE128 is GigaDevice’s 1.7–2.0V "LE" 128Mbit SPI/Quad-SPI NOR matching the 1.8V W25Q128JW/FW: same SOIC-8/WSON-8 footprint, 4KB sectors, standard command set, and QE bit (SR2 bit1), so it is a footprint+register drop-in at 1.8V. Caution: this is a 1.8V part — do NOT substitute it for a 3.3V W25Q128JV, and do not apply 3.3V to it; also update the JEDEC ID (Winbond EFh → GigaDevice C8h).

Standard SPI NOR operations (03h/0Bh read, 20h 4KB erase, 02h page-program, 9Fh JEDEC ID) and the SOIC-8 footprint are compatible. But the legacy SST25VF uses the proprietary AAI word-program (ADh) that GD25Q does not support — such firmware must switch to standard page-program; the SST26VF is a modern SFDP/SQI part with a different block-protection model. The JEDEC ID also differs (GD 0xC8). Re-validate the driver — a design-in alternative.

Same SOIC-8 footprint and compatible standard/dual-SPI command set (read, 4KB erase, page-program, JEDEC ID), so GD25Q/GD25D drops onto W25X designs that use standard or dual SPI. Note: W25X is the older Dual-SPI family while GD25Q adds Quad (SR2 QE bit), and the JEDEC manufacturer ID differs (GD 0xC8 vs Winbond 0xEF) — update any ID check and match density; GD25D is the closest non-Quad match.

ISSI IS25LP (3V) / IS25WP (1.8V) and GigaDevice GD25Q (3V) / GD25LE (1.8V) are all JEDEC-standard SPI NOR in SOP-8/WSON-8 with the standard 25-series command set and SFDP, so they swap on the same layout. Match the voltage rail (IS25LP→GD25Q, IS25WP→GD25LE — never mix) and update any hard-coded JEDEC ID (ISSI 0x9D vs GigaDevice 0xC8).

XMC (Wuhan Xinxin) XM25QH and Zbit ZB25VQ are both 3V JEDEC-standard SPI NOR in the standard SOP-8/USON footprint with the 25-series command set, SFDP, and Dual/Quad I/O, so they drop into the same socket as GD25Q. The only caveat is the JEDEC manufacturer ID (XMC 0x20, Zbit 0x5E vs GigaDevice 0xC8) if the host uses a fixed-ID lookup instead of SFDP.

Puya P25Q (e.g. P25Q16H/P25Q32H) is standard JEDEC 25-series 3V SPI NOR (2.3~3.6V, SPI mode 0/3, 4KB sector/64KB block, Dual/Quad, 9Fh JEDEC ID) in SOP-8, so it drops onto the same GD25Q footprint. The only caveat: firmware that hard-codes the JEDEC manufacturer ID must accept GigaDevice 0xC8 (Puya is 0x85), and confirm SFDP/features per density.

Adesto/Renesas AT25SF (e.g. AT25SF081/161B/321B) is standard JEDEC 25-series 3V SPI NOR (2.5/2.7~3.6V, SPI mode 0/3, 9Fh JEDEC ID, Dual/Quad) in SOIC-8, pin- and command-compatible with GD25Q on the same footprint. Caveat: update firmware that compares the JEDEC manufacturer ID (Adesto/Renesas 0x1F vs GigaDevice 0xC8) and confirm matching density/features.

Both are SPI NAND with the same command framework, page size, and WSON-8 footprint, but not a transparent drop-in: Winbond and GigaDevice differ in on-die ECC strength, ECC-status bit encoding, spare-area parity layout, and bad-block/OTP handling, so the MTD/flash driver and ECC-status parsing must be adapted. Verify ECC config, spare-area map, bad-block scheme, voltage, and timing per datasheet.

Macronix MX35 and Micron MT29F 1Gb SPI NAND share the common SPI-NAND command set (e.g. 13h page-read-to-cache) and package with the GD5F1GQ, but bad-block handling, spare/OOB layout, and on-die ECC behaviour differ per vendor, so the host NAND/MTD driver must be re-parameterised (ECC config, OOB map). Same pinout but firmware changes needed — not a blind drop-in.

Standard 24Cxx I²C interface and common pinout (SOP8 / TSSOP8 / DIP8) — a drop-in for AT24C, 24LC, and M24C parts. Confirm voltage and write timing per density.

FT93C46/56/66 is a standard 3-wire Microwire serial EEPROM in SOIC-8, pin-for-pin with the AT93C46 including the ORG pin (ORG=VCC → x16 words, ORG=GND → x8). The decisive caveat is word organization: confirm whether the design uses x8 or x16, and whether the original part actually has an ORG pin (some "93C46A"/fixed-organization variants are x16-only or repurpose that pin). Also confirm voltage (2.7–5.5V vs a 1.8V variant) and clock timing.

The FMD FT25C is a standard 25-series SPI EEPROM (20MHz, 1.8~5.5V, SOIC-8/TSSOP-8/DIP-8) with the standard WREN/WRITE/READ/RDSR/WRSR command set and AT25-compatible pinout, so it drops in for the same density. Confirm the density code and page-write size (e.g. 32-byte page) match the original and check WP/HOLD pin usage; do not replace a larger part with a smaller one.

The EM4200 is EM Microelectronic’s designed direct replacement for the EM4100/4102 read-only ICs and is protocol-compatible: an existing 125kHz reader decodes an EM4200-programmed tag exactly like an EM4100/TK4100 (same Manchester / 64-bit ID framing), with EM4200 adding higher density and longer read range. For read-side interchange it is a functional drop-in.

T5577 and EM4305 are both 125kHz read/write LF transponders, and most reader/writers list support for both — but they are not register- or command-identical: memory maps, config/control words, and password modes differ, so a reader must select the correct chip profile and a tag programmed for one is not automatically a substitute for the other. A functional, profile-specific alternative.

The W6100 is a pin-compatible upgrade of the W5100S — same hardwired TCP/IP architecture plus IPv4/IPv6 dual-stack. Check the new registers if you enable IPv6 features.

Not a drop-in, but a common design alternative: W5500 has hardwired TCP/IP, 8 sockets, and a 32KB buffer; ENC28J60 is a 10Mbps MAC+PHY with an 8KB buffer that needs a software stack. Moving to W5500 offloads the MCU.

A peer alternative — both are SPI MAC+PHY that need a software stack. DM9051 is 10/100M with 16KB SRAM and checksum offload (with an official ESP32 reference design). Different pinout/driver, so it is a design-in alternative.

The DM9000 is the common modern successor for legacy parallel/ISA-style 10/100 Ethernet+PHY controllers, but it is not pin- or register-compatible with the CS8900A or RTL8019AS: the DM9000 uses its own index/data-port bus and register set, so both the PCB interface and the driver must be redesigned. A migration-path alternative (re-layout + new driver), not a drop-in.

The LAN8720A and DM9162 are both standard 10/100 Ethernet PHYs managed over MDIO/MDC (clause-22), so they interchange behind an RMII MAC. But the pinout/package and vendor extended registers differ — a re-layout and PHY driver/init change are required, so it is a design-in alternative. Use the RMII-capable (50MHz) DM9162, not the MII-only DM9161A.

The DP83848 is a 48-LQFP MII/RMII 10/100 PHY; like the DM9162 it is managed over MDIO (clause-22) and is interchangeable behind an MII/RMII MAC, but its pinout and TI-specific registers differ — a design-in replacement (re-layout + PHY init change), not a drop-in. The DM9162 supports both MII and RMII.

The RTL8201F, IP101G, and DM9162 are all standard MII/RMII 10/100 PHYs managed over MDIO (clause-22), interchangeable at the MAC interface, but each has its own pinout/package and vendor registers — a design-in replacement needing re-layout and a PHY driver change, not pin-compatible. The DM9162 provides the RMII interface these parts use.

The KSZ8081 and DM9162 are both standard 10/100 PHYs managed over IEEE 802.3 clause-22 MDIO, so a generic MAC driver reads the standard registers the same way. But the KSZ8081 is RMII-only in a 24/32-pin QFN with a different pinout and Micrel/Microchip vendor registers, so a re-layout and PHY driver/strap review are required — not pin-compatible. Use the RMII-capable DM9162.

The LAN8742A is the very common default STM32 (H7/F7 Nucleo) PHY, RMII-only in a 24-pin SQFN. Like the DM9162 it is clause-22 MDIO-managed and interchangeable behind the same MAC, but its pinout and vendor registers differ — a re-layout and PHY init change are needed; both being RMII does not make it pin-compatible, so it is a design-in alternative.

The KSZ8041 supports MII/RMII with clause-22 MDIO, so the DM9162 is a functional alternative, but the KSZ8041 is a 32-pin QFN / 48-LQFP with a different pinout and Micrel registers. Note: the KSZ8041NL needs an external 50MHz RMII clock whereas the KSZ8041RNL/DM9162 can output 50MHz from a 25MHz reference; design-in and driver review required.

Not pin-compatible: the RV-3028-C7 is an ultra-low-power I²C RTC (~45nA timekeeping vs DS3231 ~840nA, PCF8563 ~250nA) for battery devices. DS3231 keeps a wide-temperature TCXO edge; a firmware port is needed.

AB1805, AM1805, and RV-1805-C3 are all built on the same Ambiq AM18x5 ultra-low-power RTC core with an identical register map and I²C/SPI command set (one driver serves all three), so firmware ports unchanged. They are not a pin/footprint drop-in, however: the RV-1805-C3 uses Micro Crystal’s own small module package versus Abracon/Ambiq’s 16-VFQFN, so a re-layout is required. Note: the RV-1805-C3 is NRND — for new designs consider the RV-3028-C7.

The RV-8564 is register/command compatible with the PCF8563: the same 16-register map with auto-increment, the same I²C address (0xA2), and 400kHz Fast-Mode, so PCF8563 firmware runs unchanged (Linux uses one driver for both). It is not pin-compatible, however — the RV-8564 is a leadless ceramic module with embedded crystal (C2 SON-10 5.0×3.2mm, C3 3.7×2.5mm), so the PCF8563 SOIC-8 footprint must be re-laid-out.

The DS1307 and RV-8564 are not interface-compatible: the DS1307 uses I²C address 0x68 with a different register layout, is 5V-only with an external crystal and no alarm, whereas the RV-8564 is at 0xA2, 1.2~5.5V with an embedded crystal, alarm, and timer. Both firmware and PCB must be reworked — a functional alternative, useful when migrating off the older/5V DS1307.

The PCF85063A and RV-3028-C7 are both small I²C RTCs, but they are not register-compatible: the I²C address differs (0x51 vs 0x52) and the time-register offset differs (04h vs 00h), plus the RV-3028 adds EEPROM-stored config, a UNIX-time counter, and automatic backup switchover. A new driver is required — a functional alternative whose selling point is ultra-low power (~45nA).

The M41T81 and DS1338 use a Dallas/ST register map at I²C address 0x68, whereas the RV-8564 (PCF8563-style map, address 0x51) has an entirely different address and register layout — so both the bus address and the timekeeping driver must change. A functional design-in replacement, not pin- or register-compatible. The RV-8564’s clock+SRAM feature set maps most naturally to these basic RTCs.

The HYM8563 is a PCF8563-compatible clone (same I²C address 0x51/A2h, same 16-register map, shares the Linux pcf8563 driver); the RV-8564 is likewise PCF8563-compatible (A2h/A3h, identical register map), so existing PCF8563/HYM8563 firmware runs unchanged. It is software-compatible but not a footprint drop-in: the RV-8564 is a self-contained SMD module with embedded 32.768kHz crystal, so the PCB must be re-laid for the module (and the external crystal removed).

The SD2405 (whwave) and RV-3028-C7 are both I²C RTC modules with an embedded crystal, but not interchangeable at the bus level: the SD2405 uses address 0x32 with its own ~32-register map (and an on-chip backup battery), while the RV-3028-C7 uses 0x52 with a completely different register map, EEPROM-based config, a 32-bit UNIX-time counter, and a trickle charger. Firmware must be rewritten — a functional design-in alternative.

Abracon ABS07, Epson FC-135, and the CM8V-T1A are all 32.768kHz tuning-fork crystals with overlapping load-capacitance options (the CM8V-T1A offers 4.0/7/9/12.5pF), so frequency and CL can be matched. But the footprint differs — the CM8V-T1A is 2.0×1.2mm while ABS07/FC-135 are 3.2×1.5mm — so it is not a drop-in: the 2-pad land pattern must be re-laid out and the load capacitance matched to the original.

A second source for the industry-standard TO-220 / TO-263 5-pin buck regulators — same pinout and fixed/adjustable options. Compare thermal and switching specs against the original before mass production.

The WizFi360 is widely used as a footprint-compatible alternative to ESP8266 / ESP-12F — 2.4GHz 802.11b/g/n with an AT-command interface. Confirm pin mapping and AT command-set differences before swapping.